VLSI – Real and practical steps to build chip with minimum Signal Integrity issues!!
Performance, Power and Area are the three main pillars of the Chip Design, Crosstalk can hamper all three.
What you’ll learn
- To Learn Chip Design with minimal Crosstalk in the circuits..
- To Design a Chip with minimal errors..
Course Content
- Introduction –> 1 lecture • 8min.
- Crosstalk – Why and How Crosstalk occurs in a CHIP ?? –> 6 lectures • 56min.
- Glitch Examples And Factors Affecting Glitch Height –> 7 lectures • 1hr 9min.
- Tolerable Glitch Heights and Introduction to AC Noise Margin –> 7 lectures • 1hr 5min.
- Timing Windows –> 5 lectures • 47min.
- Crosstalk Delta Delay Analysis –> 7 lectures • 1hr 5min.
- Noise Protection Technique –> 3 lectures • 29min.
- Power Supply Noise And Power Mesh Solution –> 5 lectures • 47min.
- Summary –> 1 lecture • 8min.
- Quiz and Evaluation –> 0 lectures • 0min.
Requirements
Performance, Power and Area are the three main pillars of the Chip Design, Crosstalk can hamper all three.
Crosstalk is the interference caused due to communication between the circuits
Lets learn to ” HOW TO REDUCE CROSSTALK ? ” to achieve a efficient Chip design which give the best performance, uses optimal power and in minimal Chip area.
Course Details:
•Reasons for Crosstalk
•Introduction to Noise Margin
•Crosstalk Glitch Example
•Factors Affecting Glitch Height
•AC Noise Margin
•Timing Window Concepts
•Impact of Crosstalk on Setup and Hold Timing
•Techniques to reduce Crosstalk
•Power Supply Noise